30.08.19

Error (12153): Can't Elaborate Top-level User Hierarchy

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1. Error (12153): Can't Elaborate Top-level User Hierarchy Examples
2. Error (12153): Can't Elaborate Top-level User Hierarchy Pdf

I have a verilog as module I get the error

Error (10137): Verilog HDL Procedural Assignment error object 'result' on

Give the instance a different name than the module. Your code is a good copy of the data on pastebin, but what is snake supposed to do? Is it actually a shift register that should fill and then empty? Goku super saiyan 3 games full. It seems like Quartus II could not identify the top level file during compilation. Attachments: Only certain file types can be uploaded. If you upload a file that is not allowed, the 'Answer' button will be greyed out and you will not be able to submit.

left-hand side of assignment must have a variable data type

If I add also reg [31:0] result;, I get another error

Code:

Edited code:

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2 Answers

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You have declared result in you module declaration to be of type wire. You can't assign values to wires in always blocks.

Instead you should declare result as the correct type as explained in this StackOverflow question (thanks @Greg).

This makes it of reg type which can be assigned in an always block.

However, this is not your only problem. You are assigning values to temp_reg in two different always blocks. This is not allowed. You can only have one driver (one always block or assign statement) for any signal. Otherwise how can it implement it in logic.

You can fix this by doing:

Tom Carpenter

Error (12153): Can't Elaborate Top-level User Hierarchy Examples

Tom Carpenter$endgroup$$begingroup$

You need result to be a reg. If you want to continue using non-ANSI then use:

For ANSI header use:

tempreg as being assigned in two always blocks, which is not sunthesizable. always @(type) and always @(!type) are not working the way you are thinking. Both will trigger on a change of value, but the value itself doesn't matter. Combine into one always @* (we are no longer in 1995, we don't have do list the full sensitivity list).

You should be using always @* (or the synonyms always @(*)) for all combinational logic blocks, and using blocking (=) assignments instead of non-blocking (<=). Non-blocking should be used for assigning flip-flops and latches, everything else should be blocking.

Make sure every bit of tempreg is assigned a value in one pass of the always block. Otherwise, you are inferring level sensitive latches.

Edit:
Looking at your code again, your going to need a clock. tempreg is storing values and will not be purely combinational logic. Use the template below, and use non-blocking assignments to tempreg. If you don't use the clock, then you will have complex latching logic. If you don't use non-blocking, then there is a potential race condition in the Verilog simulator.

I advice you looking into ANSI style headers. Also, try not to use type as a variable name, it is not forward comparable with SystemVerilog.

Error (12153): Can't Elaborate Top-level User Hierarchy Pdf

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